1. Field of the Invention
The present invention relates to the general field of methods for making metal interconnections for integrated circuits on semiconductor substrates, and more particularly relates to methods for forming metal interconnections on topographically uneven substrates or bases.
2. Description of The Prior Art
Integrated circuits formed on semiconductor substrates often require multiple levels of metal interconnections for electrically interconnecting electronic devices on semiconductor chips. As multiple layers of the metallic connections are built up, the topography of the semiconductor chip becomes uneven, resulting in an irregular or substantially non-planar surface for laying down subsequent metallic layers. Such topographical irregularities lead to photoresist being placed on the surface at different heights. This increases difficulties in exposing the photoresist because having the photoresist at different elevations makes it difficult to properly focus exposure light from a light source on the photoresist for accurate exposure in a photolithography process. In addition, linewidth variations may result, from well known standing wave effects. For photolithographic processes which require a shallow depth of focus during exposure of the photoresist, unwanted distortions of photoresist images may occur when the photoresist is exposed over the uneven topography. In addition, problems associated with the uneven topography are exacerbated as thinner layers of photoresist are used. Such thinner layers of photoresist have been proposed as part of photolithography systems involving exposure by light having wavelengths from 11 nm to 14 nm, or by light from F2 exposure by light having wavelengths from 11 nm to 14 nm, or by light from F2 excimer lasers having wavelengths of approximately 157 nm, for example. Uneven distributions of photoresist due to the irregular surface topography lead to poor performance of the photoresist because the shorter-wavelength light used to expose the thin photoresist does not penetrate the photoresist as well as longer-wavelength light. Therefore, the uniformity of photoresist thickness takes on added importance when shorter-wavelength light is used for exposure.
Intervening layers of material have been used between the conducting material and the photoresist in part to reduce the effects of the uneven topography and in part for their usefulness in the etching process of the underlying metallic layer. However, such layers do not eliminate the problem of uneven topography, but at best merely reduce it to some degree.
Another approach to circumventing topographic problems has been to provide essentially planar insulating layers on which each layer of metal is then deposited. Such methods, however, have the disadvantage of requiring complex series of steps that include planarizing the insulating layer, planarizing the metal surface, and using metal plugs to fill in contact openings in the thick insulating layers of the resulting structure.
Another prior method for partially overcoming the problems of uneven topography are known as multilayered resist (MLR) processes. In MLR processes, an organic resist layer is first spun onto the wafer, thicker than the unevenness of the underlying topography, to provide a surface which is smoother and more planar than the original topography. An optional intermediate oxide or other inorganic film may then be deposited on the thick resist layer. The oxide is used as an etch mask for the thick layer. Finally, a thin imaging resist layer is deposited on top of the planarized stack. MLR has the drawback of adding steps to the production process, thereby degrading productivity.
From the foregoing it will be appreciated that there is a need in the semiconductor industry for providing a simple method of addressing the problems associated with uneven topography due to deposit of multiple metallic layers.
A method of forming a conductor pattern on a base with uneven topography includes placing conductor material on the base, placing a hard mask material on the conductor material, planarizing an exposed surface of the hard mask material, and placing a layer of resist on the hard mask material. The resist is patterned and the patterned resist is used in selectively etching the hard mask material, with the hard mask material used in selectively etching the underlying conductor material. By planarizing the hard mask material prior to placing a layer of resist thereupon, uniformity of the resist coating is enhanced and depth of focus problems in exposing the resist are reduced.
According to an aspect of the invention a method of forming a conductor pattern on a substrate with uneven topography includes planarizing a surface of a hard mask material which overlies the conductor material.
According to another aspect of the invention, a method of forming a conductor pattern on a base with uneven topography includes the steps of: (1) depositing a hard mask layer on top of a conductor layer which is on the base; (2) planarizing a surface of the hard mask layer; (3) placing a layer of resist on the surface of the hard mask layer; (4) patterning a resist pattern onto the resist; and (5) patterning the conductor layer, using the resist pattern and the hard mask layer, to form the conductor pattern.
According to yet another aspect of the invention, a method of forming a conductor pattern on a base with uneven topography includes the steps of: (1) depositing a conductor layer on the base, the conductor layer having uneven topography corresponding to the uneven topography of the base; (2) depositing a hard mask layer on top of a conductor layer which is on the base, the hard mask layer having uneven topography corresponding to the uneven topography of the conductor layer; (3) planarizing a surface of the hard mask layer; (4) placing a layer of resist on the surface of the hard mask layer; (5) patterning a resist pattern onto the resist; and (6) patterning the conductor layer, using the resist pattern and the hard mask layer, to form the conductor pattern.
According to still another aspect of the invention, a method of forming a resist layer on an underlying layer includes the steps of planarizing the underlying layer, and coating the underlying layer with resist.
According to a further aspect of the invention, a method of forming a semiconductor device includes planarizing a surface upon which resist is to be deposited.